1. Field of the Invention
The present invention generally relates to a method of operating a plasma display panel and a display device using such a method. More particularly, the present invention relates to a method of operating a plasma display panel constructed by a set of cells (display elements) each having a memory function, and a plasma display device using such a method. Specifically, the present invention concerns an operating method for writing display data in an AC plasma display panel, and a plasma display device in which such an operating method is used.
In an AC plasma display panel, an alternating voltage is applied between two sustain electrodes so that a discharge is sustained and illuminated display is effected. A cycle of discharge ends 1- to 10-.mu.s after a pulse is applied. Ions (positive charges) created by the discharge are collected on the surface of an insulating layer on the electrode to which a negative voltage is applied. Electrons (negative charges) are collected on the surface of an insulating layer on the electrode to which a positive voltage is applied.
After a pulse (write pulse) having a relatively high voltage (write voltage) is applied so that a write discharge is performed and wall charges are formed, a pulse (sustain pulse) having an opposite polarity and having a relatively low voltage (sustain discharge voltage) is applied. Charges created by applying the sustain pulse are superimposed on the wall charges. As a result, the voltage with respect to the ambient space grows to exceed a threshold voltage so that a discharge occurs. To summarize the above, once the write discharge is performed so that the wall charges are created, the discharge is sustained by applying alternating sustain pulses. This phenomenon is referred to as a memory effect or a memory function. In general, the AC plasma display panel displays by utilizing the memory effect.
A cell in which a discharge takes place is separated from the adjacent cells by ribs or barriers. Ribs or barriers may be provided to surround on all four sides a cell in which a discharge takes place. Alternatively, a rib or a barrier may be provided to cover one of the four sides of the cell so that, on the remaining three sides, the cell is separated from the adjacent cells by optimizing gaps between electrodes.
The present invention provides a surface-discharge AC plasma display panel using three electrodes in a cell. The technology provided by the present invention is most suitably used when the write discharge (address discharge) for selection of a cell in correspondence with display data is performed in a panel constructed such that a barrier is provided to cover only one of the four sides of the cell. The technology described hereinafter is particularly useful to advance the development of high-brightness, high-precision and large-scale display panel.
2. Description of the Related Art
Two types of conventional AC plasma display panels are known: a dual-electrode plasma display panel in which two electrodes are used to perform an address discharge and a sustain discharge; and a triple-electrode plasma display panel in which three electrodes are used to perform the address discharge. In a dual-electrode plasma display panel used as a color display panel capable of display gradations, a fluorescent body (phosphor) formed in a cell is excited by an ultraviolet ray created by the discharge. Since positive ions generated in the discharge directly impinges upon the fluorescent body susceptible to impact of positive ions, the life of the fluorescent body is relatively rapidly exhausted.
For this reason, a triple-electrode surface-discharge AC plasma display panel is normally used as a color display panel. A triple-electrode surface-discharge AC plasma display panel may be constructed such that a third electrode is formed on the same substrate on which first and second electrodes selected for the sustain discharge are formed. Alternatively, the triple-electrode surface-discharge AC display panel may be constructed such that a third electrode is formed on a separate substrate facing the substrate on which the first and second electrodes are formed.
The plasma display panel in which the three electrodes are formed on the same substrate may be constructed such that the third electrode is provided above the two electrodes for the sustain discharge. Alternatively, the third electrode may be formed below the two electrodes for the sustain discharge.
According to another classification, a plasma display panel may be a transparent plasma display panel constructed such that visible light emitted and transmitted by the fluorescent body is observed human eyes. A reflection plasma display panel is constructed such that the reflection from the fluorescent body is observed.
A description will now be given of a conventional reflection triple-electrode surface-discharge AC plasma display panel in which the third electrode is formed on a substrate facing the substrate on which the electrodes for the sustain discharge are formed, ribs are formed only in an orthogonal direction (that is, in a direction perpendicular to the direction in which the sustain electrodes lie and parallel to the direction in which the third electrode lies), and each of the sustain electrodes is formed in part by a transparent electrode.
FIG. 1 shows such a conventional reflection triple-electrode surface-discharge AC plasma display panel 2. FIG. 2 shows another triple-electrode surface-discharge AC plasma display panel 2 which is an elaboration of the panel of FIG. 1 in that the disposition of the electrodes is improved so that the capacitance between electrodes is reduced. FIG. 3 is a sectional view of the triple-electrode surface-discharge AC plasma display panel of FIGS. 1 and 2 taken along the direction in which the third electrodes lie. FIG. 4 is a sectional view of the plasma display panel of FIGS. 1 and 2 taken along the direction in which the sustain electrodes lie.
As shown in FIGS. 3 and 4, the triple-electrode surface-discharge AC plasma display panel of FIGS. 1 and 2 includes two glass substrates (more specifically, a rear glass substrate and a front glass substrate).
A first electrode 207 (specifically, X electrode) and a second electrode 208 (specifically, Y electrode) are formed in the front glass substrate 205 with a separation of a discharge slit (that is, a gap between the X electrode 207 and the Y electrode 208 set to about 100 .mu.m). A pair formed by the first electrode 207 and the second electrode 208 constitutes a sustain electrode. Each of these electrodes 207, 208 is composed by a transparent electrode 207A and a bus electrode 207B. The transparent electrode 207A lets a reflected beam 207H from a fluorescent body 207 to pass therethrough. The bus electrode 207B is provided to prevent a voltage drop by an electrode resistance. In addition, the electrodes are coated by a dielectric layer 207C and a MgO (magnesium oxide) film 207D is formed on the discharge side as a protective film. Moreover, a third electrode (address electrode) 209 is formed in the second substrate 206 (specifically, the rear glass substrate 206) opposite to front glass substrate 205 so as to be orthogonal to the first electrode 207. Moreover, a barrier 207E is formed between the address electrodes 209 protected with a dielectric 207G. A fluorescent body 207F with a red, green, blue luminescence characteristic is formed so as to cover the address electrode 209 between the barriers 207E. The rear glass substrate 206 and the front glass substrate 205 are assembled such that a ridge of the barrier 207E and the MgO film 207D are in close contact with each other. Moreover, when the discharge slit between the first electrode 207 and the second electrode 208 which form the pair is set to 100 .mu.m, a non-discharge slit which is a gap between two adjacent sustain electrodes in the respective display lines is set to 300 .mu.m. The width of the sustain electrode is set to about 250 .mu.m.
FIG. 5 is a block diagram of a conventional plasma display device 9 where a peripheral circuit to drive the plasma display panel of FIG. 1 and FIG. 2 is provided. An address pulse for the address discharge is applied to the address electrode 209 using an address driver 28 connected to each of address electrode 209 in the plasma display device 9. The address driver 28 is controlled by a control circuit 281. Moreover, the Y electrode 208 is individually connected to a scan driver 27 (Y scan driver 27).
The Y scan driver 27 is connected to a Y-side common driver 22. The pulse for the address discharge is generated by the scan driver 27. The sustain pulse etc. are generated by the Y-side common driver 22. These pulses are applied to the Y electrode 208 via the Y scan driver 27. The Y-side common driver 22 is controlled by a common driver control unit 221 provided in a panel operation control unit 281A. The Y scan driver 27 is controlled by a scan driver control unit 271 provided in the panel operation control unit 281A.
The X electrode 207 is connected together in the entire display lines 201 of a plasma display panel 2. A X-side common driver 22 (not shown) generates the write pulse, the sustain pulse, etc. and is controlled by the common driver control unit 221. The common driver control unit 221, the scan driver control unit 271, and the control circuit 281 are controlled with a vertical sync signal (VSYNC in FIG. 5) and a horizontal sync signal (HSYNC in FIG. 5) input from outside the device to the panel operation control unit 281A, and with a display data signal (DATA in FIG. 5) and a dot clock (CLOCK in FIG. 5) input to a display data control unit 281B. The display data signal DATA input according to the dot clock CLOCK is stored in a frame memory 281B-1.
FIG. 6 is a waveform chart which shows a conventional method of operating the plasma display panel 2 shown in FIGS. 1-4 with the circuit shown in FIG. 5. The chart illustrates one sub-field period in the separated address period/sustain discharge period write addressing.
One sub-field in the conventional method is divided into a reset period, an address period, and a sustain discharge period. All the Y electrodes 208 are first set at a 0 V level and an whole-screen write pulse of a Vs+Vw (specifically, about 300 V) is applied to the X electrodes 207 at the same time for the reset period. The discharge is caused in all cells of all the display lines 201 regardless of the previous state of the display. A potential Vaw of the address electrode 209 at this time is about 100 V. Next, the potential of the X electrode 207 and the address electrode 209 becomes 0 V. In all cells, the voltage due to a wall charge 204 exceeds a discharge-initiating (firing) voltage and the discharge is begun. The space charge is self-neutralized and the discharge ends, since this discharge does not involve the potential difference between the electrodes. That is, a so-called self-erase discharge occurs. All cells in the panel enters a uniform state without the wall charge 204 built up, as a result of this self-erase discharge. The resetting has an action by which all cells are in the same state regardless of the previous state of the sub-field. As a result, it is possible to perform a subsequent address discharge (that is, the writing) in a stable manner.
Next, the line sequential address discharge is caused in the address period according to the display data to control the activating of the cell. FIGS. 7A-7C show the mechanism of this address discharge.
A scan pulse 21 at a -VY level (specifically, about -150 V) is applied to the Y electrode 208. An address pulse of a voltage Va (specifically, about 50 V) is selectively applied to address electrode 209 corresponding to the cell which is activated for illumination, that is the cell which is a target for the sustain discharge. The discharge occurs between the address electrode 209 and the Y electrode 208 of the cell which is lighted (see FIG. 7A). Next, this discharge triggers the discharge between the X electrode 207 and the Y electrode 208 as a priming discharge (see FIG. 7B). As a result, the wall charge 204 of an amount by which the sustain discharge is enabled is collected on the MgO film 207D on the X electrode 207 and the Y electrode 208 of the selected line 202 (see FIG. 7C). A similar operation is executed one by one for the other display lines 201. In all the display lines 201, new display data is written. Afterwards, in the sustain discharge period, the sustain pulse having a voltage of Vs (about 180 V) is alternately applied to the Y electrode 208 and the X electrode 207 so that the sustain discharge is caused. The image of one sub-field field is displayed. In this "separated address period/sustain discharge period write addressing", the duration of the sustain discharge period determines the brightness. That is, the brightness depends on the frequency of the sustain pulse (voltage Vs).
FIG. 8 is a time chart showing the sequence of the separated address period/sustain discharge period write addressing of FIG. 6.
In the separated address period/sustain discharge period write addressing, one frame is divided into eight sub-fields SF8 SF1, SF2, SF3, SF4, SF5, SF6, and SF7. In these sub-fields SF1-SF8, the reset period and the address period have the same duration. Moreover, the ratio of the durations of the sustain discharge period is 1:2:4:8:16:32:64:128. Therefore, by selecting the sub-field to be lighted, it is possible to display the brightness of 256 steps from 0 to 255. That is, a 256-step gradation display is enabled.
Specifically, one frame has the duration of 16.6 ms (1/60 Hz) assuming that the cycle of rewriting the screen is 60 Hz. Moreover, when the pulse frequency in one frame of the sustain discharge (referred to as the sustain cycle) is assumed to be 510 times per frame, 2 cycles occur in the sub-field SF1, 4 cycles occur in the sub-field SF2, 8 cycles occur in the sub-field SF3, 16 cycles occur in the sub-field SF4, 32 cycles occur in the sub-field SF5, 64 cycles occur in the sub-field SF6, 128 cycles occur in the sub-field SF7, and 256 cycles occur in the sub-field SF8. When duration of the sustain cycle is assumed to be 8 ms, the total duration in one frame becomes 4.08 ms. About 12 ms of the remainder is allocated for the eight reset periods, address periods, and stop periods. Therefore, the reset period and the address period of each sub-field have the duration of about 1.5 ms. When it is assumed that about 50 ms is necessary for the reset period of each address period, the address cycle becomes 3 ms to drive the panel of 500 lines.
However, high-brightness, high-resolution, and large scale design can be achieved in the plasma display device 9 which uses the above-described conventional method, by connecting the X electrode 207 with a common bus to provide an easy leading out of the panel electrode to the circuit side and the simplification of the circuit. As a result, though the Y electrode 208 and the address electrode 209 are fed the selection potential or the non-selection potential, no stable operation is enabled because the X electrode 207 is connected to the common bus.
A further explanation will now be given of the problem in making a high-resolution plasma display device 9 which uses a conventional method of operating a plasma display panel. The explanation will be given based on the construction of the plasma display panel 2 shown in FIGS. 1-4. It is to be noted that raising the brightness by raising the frequency of lighting has a limitation in terms of the power consumption, the time distribution and the life of the device. Hence, it is necessary to raise the lighting efficiency.
One method of raising the lighting efficiency is to allow the discharge to be conducted within a wide range and to positively activate the discharge. Narrowing the discharge slit (that is, the gap between the transparent electrode 207A of the X electrode 207 and the Y electrode 208) to only a limited degree and enlarging the width of the transparent electrode 207A are advantageous to allow the discharge to be conducted within a wide range. Another method is to increase the numerical aperture so that the beam generated in the fluorescent body 207F is led to the surface without much disturbance. In the case of the reflection device, it is desirable that the width of the bus electrode 207B be relatively small because the bus electrode 207B presents an obstruction to the reflected beam 207H. However, the resistance element of the electrode is increased when the width of the bus electrode 207B is narrowed too much, increasing the voltage drop when the discharge current flows. As a result, the voltage applied to the cell decreases, the activation of the discharge is disturbed consequently, decreasing the brightness. Moreover, the amount of the voltage drop depends on the magnitude of a display area. Therefore, a change in the magnitude of the display area brings about a change in the brightness, significantly reducing the display quality occasionally.
Considering above-mentioned point, it is preferable to enlarge the width of the transparent electrode 207A and to narrow the bus electrode 207B only to a limited degree. As a result, the non-discharge slit on the reverse side with respect to the discharge slit will become narrow under a given size of the cell. When the non-discharge slit is too narrow, the discharge-initiating voltage for the discharge slit and that for the non-discharge slit approaches (the discharge-initiating voltage is determined depending on the product of the distance and the gas pressure between the electrodes as well as on the composition of the enclosed gas, the dielectric substance material, and the quality of MgO film 207D), so that the cells are prevented from being properly separated from each other. There is known a plasma display panel in which the stripe barrier 207E is formed in the non-discharge slit so as to separate the cells (that is, the discharge space) properly.
Providing the stripe barrier 207E in the non-discharge slit prevents making of a plasma display panel 2 of high resolution and will make it difficult to manufacture the plasma display panel 2 with precision. The barrier 207E is often formed with the thick-film print technology (screen print technology) and the sand blasting. Providing the stripe barrier 207E of a width on the order of 10-100 .mu.m and a height on the order of 100-200 .mu.m is very difficult compared with providing the barrier 207E only in one direction. Moreover, the accuracy required when front glass substrate 205 carrying the first electrode 207 and the rear glass substrates 206 carrying the address electrode 209 are attached to each other can be less strict so that the high resolution can be achieved if the stripe barrier 207E is provided only in one direction than the accuracy required when the stripe barrier 207E is provided.
In addition, when the high resolution is intended, this stripe barrier 207E is a factor making the process for manufacturing the plasma display panel 2 more difficult Moreover, even if the stripe barrier 207E is not provided, it is necessary to narrow the non-discharge slit if the high resolution is intended. In the plasma display panel 2 characterized by a narrow non-discharge slit, the space charge freely extends to the space in the vertical direction, and an unnecessary effect of the priming is generated for the cells adjoining in the vertical direction, resulting in unnecessary collection of the wall charge 204. As a result, an improper discharge (mis-addressing) is generated. Such a phenomenon is called a vertical connection.
Next, the generation mechanism of the vertical connection is explained with reference to FIGS. 7A-7C. The address discharge to select the display cell is caused by giving the voltage of less than the minimum discharge-initiating voltage and more than the minimum sustain discharge voltage to the X electrode 207 and the Y electrode 208, and by giving, to the address electrode 209 forming the cell to be selected, the address pulse (voltage Va) of a level by which the potential difference with respect to the Y electrode 208 exceeds the discharge-initiating voltage between the address electrode 209 and the Y electrode 208.
The voltage of VX (50 V) is applied to the X electrode 207 as shown in FIGS. 7A-7C. Moreover, the scan pulse 21 of the selection potential -VY (-150 V) is applied to the Y electrode 208. At this time, the address pulse of Va (50 V) (voltage Va) is applied to the address electrode 209 of the cell selected for the discharge so that the discharge is begun. Here, when the discharge-initiating voltage between the address electrode 209 and the Y electrode 208 is assumed to be VfAY, the relation of VfAY.ltoreq.Va+VY (=200 V) exists. Moreover, when the minimum sustain discharge voltage between the X electrode 207 and the Y electrode 208 is assumed to be Vsm and the discharge-initiating voltage between the X electrode 207 and the Y electrode 208 is assumed to be Vf, the relation of Vsm.ltoreq.VX+VY (200 V)&lt;Vf exists.
The discharge begun between the address electrode 209 and the Y electrode 208 (the first step) triggers and activates the discharge between the X electrode 207 and the Y electrode 208 (the second step). When the discharge is settled in the final (the 3rd) stage, the negative wall charge 204 is collected on the X electrode 207 side, the positive wall charge 204 is collected on the Y electrode 208 side, and the negative wall charge 204 is collected on the address electrode 209 side, respectively.
Next, a description will now be given of an influence on the adjacent lines. FIGS. 9 through 12 are referred to for an explanation of the influence on the adjacent cells occurring in the address discharge.
Referring to FIGS. 9 through 12, three cells consecutive in the vertical direction are formed by an X1 electrode 207-l and a the Y1 electrode 208-1, an X2 electrode 207-2 and a Y2 electrode 208-2, and an X-3 electrode 207-3 and a Y3 electrode 208-3, respectively.
FIG. 9 shows that the address discharge is not caused in the cell formed by the electrode 208-1 since display data is not supplied thereto and that the address discharge is caused in the cell of the Y2 electrode 208-2. The voltage applied to the X1 electrode 207-1 adjacent to the Y2 electrode 208-2 is the same as the voltage vX (50 V) applied to the X electrode 207 of the selected line 202. Negative charges are drawn to the Y2 electrode 208-2 naturally since this voltage has a positive polarity so that the drawn charges are collected as the wall charge 204. When the wall charge 204 collected on the X1 electrode 207-1 is small in volume, it does not present any problem when the non-discharge slit is as wide as 300 .mu.m as shown in FIG. 9.
However, as the cell pitch becomes small as shown in FIG. 10 so that the non-discharge slit is as narrow as, for instance, 200 .mu.m, the wall charges 204 is collected in a large amount on the X1 electrode 207-1 side. When the minimum sustain discharge voltage between the X1 electrode 207-1 and the Y2 electrode 208-2, that is, the minimum sustain discharge voltage in the non-discharge slit, is 190 V, the discharge between address electrode 209 and the Y2 electrode 208-2 may trigger the discharge between the X1 electrode 207-1 and the Y2 electrode 208-2, forming the wall charge 204.
Moreover, as shown in FIG. 11, the discharge with a large scale occurs when the voltage (Va) of the address pulse (voltage Va) to be applied to the address electrode 209 is raised from 50 V to 70 V so as to ensure that the discharge between the address electrode 209 and the Y electrode 208 which discharge is the first step of the address discharge properly occurs. As a result, a lot of the wall charge 204 is collected on the X1 electrode 207-1 side.
Moreover, as shown in FIG. 12, the discharge with a large scale occurs when the voltage (Vx) to be applied to the X electrode 207 is raised from 50 V to 70 V so as to ensure that the discharge between the X electrode 207 and the Y electrode 208 which discharge is the second step of the address discharge properly occurs. As a result, a lot of the wall charge 204 is collected on the X1 electrode 207-1 side.
That is, there is a problem with the conventional technology in that the improper discharge occurs as a result of a large amount of negative charge collected on the X1 electrode 207-1, causing an improper discharge.
Next, an unfavorable example of the sustain discharge (vertical connection) is explained by referring to FIG. 13.
Since the cell of the X1 electrode 207-1 is OFF, the address discharge is not caused before the sustain discharge period is started in FIG. 13. The wall charge 204 collected on the X1 electrode 207-1 may reduce the potential of the X electrode and cause the discharge between X1 and Y1 when the sustain pulse of a voltage Vs (180 V) is applied to the Y electrode 208. Moreover, the potential difference between the X1 electrode 207-1 and the address electrode 209 expands due to the wall charge 204. There is a problem in that the discharge between the X1 electrode 207-1 and the Y1 electrode 208-1 is introduced as a result of a process which corresponds to the first step of the address discharge being caused between the address electrode 209 and the X1 electrode 207-1.
Next, a description will be given, by referring to FIG. 14, of the malfunction occurring when the address discharge is performed in the plasma display panel 2 with the electrode array shown in FIG. 2.
When the address discharge involving the Y1 electrode 208-1 ends, the address discharge involving the Y2 electrode 208-2 is caused. The discharge between the Y2 electrode 208-2 and the Y1 electrode 208-1 is begun before the target discharge between the Y2 electrode 208-2 and the X2 electrode 207-2 due to a triggering action of the discharge between the address electrode 209 and the Y2 electrode 208-2 initiated by the scan pulse 21 of -150 V applied to the Y2 electrode 208-2. At this time, the address cycle ends without the discharge between the Y electrode 208-2 and the X2 electrode 207-2 being started. There was a problem that the sustain discharge is not initiated in the cell comprising the Y1 electrode 208-1 and in the cell comprising the Y2 electrode 208-2.
The present invention can ensure that propagation of the space charge from the cell selected for the address discharge is small in scale by ensuring that a lower potential occurs in the non-selected X electrode than the potential of the selected X electrode This arrangement avoids an unfavorable situation in which a discharge is caused in a line not selected, or an improper discharge is caused due to collection of the wall charge.